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| 1 ltc3808 3808f no r sense tm , low emi, synchronous dc/dc controller with output tracking programmable output voltage tracking sense resistor optional spread spectrum modulation for low noise constant frequency current mode operation for excellent line and load transient response wide v in range: 2.75v to 9.8v wide v out range: 0.6v to v in 0.6v 1.5% reference low dropout operation: 100% duty cycle true pll for frequency locking or adjustment (frequency range: 250khz to 750khz) selectable burst mode ? /pulse skipping/forced continuous operation auxiliary winding regulation internal soft-start circuitry power good output voltage monitor output overvoltage protection micropower shutdown: i q = 9 a tiny thermally enhanced leadless (4mm 3mm) dfn or 16-lead ssop package one or two cell lithium-ion powered devices notebook and palmtop computers, pdas portable instruments distributed dc power systems high efficiency, 550khz step-down converter descriptio u features applicatio s u typical applicatio u + ltc3808 2.2 h 10 f v in 2.75v to 9.8v v out 2.5v 2a 47 f 3808 ta01 15k 59k 1m 187k 220pf gnd plllpf sync/mode pgood v fb i th run sw v in sense + tg bg iprg the ltc ? 3808 is a synchronous step-down switching regulator controller that drives external complementary power mosfets using few external components. the constant frequency current mode architecture with mosfet v ds sensing eliminates the need for a current sense resistor and improves efficiency. burst mode operation provides high efficiency operation at light loads. 100% duty cycle provides low dropout operation, extending operating time in battery-powered systems. the switching frequency can be programmed up to 750khz, allowing the use of small surface mount inductors and capacitors. for noise sensitive applications, the ltc3808 can be externally synchronized from 250khz to 750khz. burst mode is inhibited during synchronization or when the sync/mode pin is pulled low to reduce noise and rf interference. to further reduce emi, the ltc3808 incorpo- rates a novel spread spectrum frequency modulation technique. the ltc3808 is available in the tiny footprint thermally enhanced dfn package or 16-lead ssop package. efficiency and power loss vs load current load current (ma) efficiency (%) 100 90 80 70 60 50 power loss (mw) 10k 1k 100 10 1 0.1 1 100 1k 10k 3808 ta01b 10 v in = 3.3v v in = 5v v in = 4.2v figure 11 circuit v out = 2.5v typical power loss (v in = 4.2v) efficiency , ltc and lt are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. no rsense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5929620, 6580258, 6304066, 5847554, 6611131, 6498466. other patents pending.
2 ltc3808 3808f order part number input supply voltage (v in )........................ C 0.3v to 10v plllpf, run, sync/mode, track/ss, sense + , iprg voltages ............ C 0.3v to (v in + 0.3v) v fb , i th voltages...................................... C0.3v to 2.4v sw, sense C voltages ......... C 2v to v in + 1v (10v max) pgood ..................................................... C 0.3v to 10v ltc3808ede t jmax = 125 c, ja = 130 c/w absolute m axi m u m ratings w ww u package/order i n for m atio n w u u consult ltc marketing for parts specified with wider operating temperature ranges. (note 1) tg, bg peak output current (<10 s) ........................ 1a operating temperature range (note 2) ... C 40 c to 85 c storage ambient temperature range ... C 65 c to 125 c junction temperature (note 3) ............................ 125 c lead temperature (soldering, 10 sec) gn16 package .................................................. 300 c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sw sense C v in sense + tg bg iprg plllpf sync/mode track/ss pgood v fb i th run top view 15 de package 14-lead (4mm 3mm) plastic dfn order part number ltc3808egn gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 gnd plllpf sync/mode track/ss pgood v fb i th run sw sense C v in sense + tg bg iprg gnd t jmax = 125 c, ja = 37 c/w exposed pad (pin 15) is gnd (must be soldered to pcb) de part marking 3808 the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 4.2v unless otherwise noted. electrical characteristics parameter conditions min typ max units main control loops input dc supply current (note 4) normal operation 350 500 a sleep mode 105 150 a shutdown run = 0v 9 20 a uvlo v in = uvlo threshold C 200mv 9 20 a undervoltage lockout threshold v in falling 1.95 2.25 2.55 v v in rising 2.15 2.45 2.75 v shutdown threshold of run pin 0.8 1.1 1.4 v start-up current source track/ss = 0v 0.65 1 1.35 a regulated feedback voltage (note 5) 0.591 0.6 0.609 v output voltage line regulation 2.75v < v in < 9.8v (note 5) 0.01 0.04 %/v output voltage load regulation i th = 0.9v (note 5) 0.1 0.5 % i th = 1.7v C0.1 C0.5 % v fb input current (note 5) 9 50 na overvoltage protect threshold measured at v fb 0.66 0.68 0.7 v 3 ltc3808 3808f parameter conditions min typ max units the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 4.2v unless otherwise noted. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc3808e is guaranteed to meet specified performance from 0 c to 70 c. specifications over the C40 c to 85 c operating range are assured by design characterization, and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja c/w) note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. note 5: the ltc3808 is tested in a feedback loop that servos i th to a specified voltage and measures the resultant v fb voltage. note 6: peak current sense voltage is reduced dependent on duty cycle to a percentage of value as shown in figure 1. overvoltage protect hysteresis 20 mv auxiliary feedback threshold 0.325 0.4 0.475 v top gate (tg) drive rise time c l = 3000pf 40 ns top gate (tg) drive fall time c l = 3000pf 40 ns bottom gate (bg) drive rise time cl = 3000pf 50 ns bottom gate (bg) drive fall time cl = 3000pf 40 ns maximum current sense voltage ( ? v sense(max) ) iprg = floating (note 6) 110 125 140 mv (sense + C sw) iprg = 0v (note 6) 70 85 100 mv iprg = v in (note 6) 185 204 223 mv soft-start time (internal) time for v fb to ramp from 0.05v to 0.55v 0.5 0.74 0.9 ms oscillator and phase-locked loop oscillator frequency unsynchronized (sync/mode not clocked) plllpf = floating 480 550 600 khz plllpf = 0v 260 300 340 khz plllpf = v in 650 750 825 khz phase-locked loop lock range sync/mode clocked minimum synchronizable frequency 200 250 khz maximum synchronizible frequency 750 1000 khz phase detector output current sinking f osc > f sync/mode C3 a sourcing f osc < f sync/mode 3 a spread spectrum frequency range minimum switching frequency 460 khz maximum switching frequency 635 khz sync/mode pull-down current sync/mode = 2.2v 2.6 a pgood output pgood voltage low i pgood sinking 1ma 50 mv pgood trip level v fb with respect to set output voltage v fb < 0.6v, ramping positive C13 C10.0 C7 % v fb < 0.6v, ramping negative C16 C13.3 C10 % v fb > 0.6v, ramping negative 7 10.0 13 % v fb > 0.6v, ramping positive 10 13.3 16 % 4 ltc3808 3808f typical perfor a ce characteristics uw efficiency vs load current efficiency vs load current maximum current sense voltage vs i th pin voltage load step (burst mode operation) load step (forced continuous mode) load step (pulse skipping mode) start-up with internal soft-start (track/ss = v in ) start-up with external soft-start (c ss = 10nf) t a = 25 c unless otherwise noted. load current (ma) efficiency (%) 100 90 80 70 95 85 75 65 60 1 100 1k 10 k 3808 g01 10 v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.2v figure 11 circuit sync/mode = v in v in = 5v load current (ma) efficiency (%) 100 90 80 70 95 85 75 65 50 55 60 3808 g02 1 100 1k 10 k 10 figure 11 circuit v in = 5v, v out = 2.5v forced continuous (sync/mode = 0v) pulse skipping (sync/mode = 0.6v) burst mode (sync/mode = v in ) v out 200mv/div ac coupled i l 2a/div 100 s/div v in = 3.3v v out = 1.8v i load = 300ma to 3a sync/mode = v in figure 11 circuit 3808 g04 v out 200mv/div ac coupled i l 2a/div 100 s/div v in = 3.3v v out = 1.8v i load = 300ma to 3a sync/mode = 0v figure 11 circuit 3808 g05 v out 200mv/div ac coupled i l 2a/div 100 s/div v in = 3.3v v out = 1.8v i load = 300ma to 3a sync/mode = v fb figure 11 circuit 3808 g06 v out 1.8v 500mv/div 200 s/div v in = 4.2v r load = 1 ? figure 11 circuit 3808 g07 v out 1.8v 500mv/div 1ms/div v in = 4.2v r load = 1 ? figure 11 circuit 3808 g08 i th voltage (v) 0.5 C20 current limit (%) 0 20 40 60 100 1 1.5 3808 g03 2 80 burst mode operation (i th rising) burst mode operation (i th falling) forced continuous mode pulse skipping mode 5 ltc3808 3808f start-up with coincident tracking (v out = 0v at 0s) start-up with coincident tracking (v out = 0.8v at 0s) start-up with ratiometric tracking (v out = 0v at 0s) regulated feedback voltage vs temperature undervoltage lockout threshold vs temperature shutdown (run) threshold vs temperature maximum current sense threshold vs temperature track/ss start-up current vs temperature typical perfor a ce characteristics uw t a = 25 c unless otherwise noted. v out 1.8v v x 2.5v 500mv/div 10ms/div v in = 4.2v r ta = 590 ? r tb = 1.18k figure 11 circuit 3808 g09 v out 1.8v v x 2.5v 500mv/div 10ms/div v in = 4.2v r ta = 590 ? r tb = 1.18k figure 11 circuit 3808 g10 v out 1.8v v x 2.5v 500mv/div 10ms/div v in = 4.2v r ta = 590 ? r tb = 1.69k figure 11 circuit 3808 g11 temperature ( c) C60 0.594 feedback voltage (v) 0.596 0.598 0.600 0.602 C20 20 60 100 3808 g12 0.604 0.606 C40 0 40 80 temperature ( c) C60 2.15 2.20 2.25 input voltage (v) 2.30 2.35 2.40 2.45 C20 20 60 100 3808 g13 2.50 2.55 C40 0 40 80 v in rising v in falling temperature ( c) C60 1.00 run voltage (v) 1.05 C20 20 60 100 3808 g14 1.15 1.10 1.20 C40 0 40 80 temperature ( c) C60 115 maximum current sense threshold (mv) 120 125 130 C20 20 60 100 3808 g16 135 C40 0 40 80 iprg = float temperature ( c) C60 0.94 track/ss start-up current ( a) C20 20 60 100 3808 g17 0.96 0.98 1.04 1.02 1.00 C40 0 40 80 track/ss = 0v 6 ltc3808 3808f sync/mode pull-down current vs temperature oscillator frequency vs temperature oscillator frequency vs input voltage shutdown quiescent current vs input voltage sleep current vs input voltage track/ss start-up current vs track/ss voltage typical perfor a ce characteristics uw t a = 25 c unless otherwise noted. temperature ( c) C60 2.40 2.45 2.50 sync/mode pull-down current ( a) 2.55 2.60 2.65 2.70 C20 20 60 100 3808 g18 2.75 2.80 C40 0 40 80 temperature ( c) C60 C10 C8 C6 normalized frequency (%) C4 C2 0 4 C20 20 60 100 3808 g19 8 2 6 10 C40 0 40 80 input voltage (v) 2 C5 C4 C3 normalized frequency shift (%) C2 C1 0 2 46 8 10 3808 g20 4 1 3 5 35 7 9 input voltage (v) 2 0 2 shutdown current ( a) 4 6 8 12 46 8 10 3808 g21 16 10 14 18 35 7 9 input voltage (v) 2 70 sleep current ( a) 80 100 46 8 10 3808 g22 120 90 110 130 35 7 9 track/ss voltage (v) 0 0.84 1.00 track/ss startup current ( a) 0.88 0.2 0.4 0.6 0.7 3808 g24 0.92 0.96 1.04 0.1 0.3 0.5 7 ltc3808 3808f uu u pi fu ctio s plllpf (pin 1/pin 2): frequency set/pll lowpass filter. when synchronizing to an external clock, this pin serves as the low pass filter point for the phase-locked loop. normally, a series rc is connected between this pin and ground. when not synchronizing to an external clock, this pin serves as the frequency select input. tying this pin to gnd selects 300khz operation; tying this pin to v in selects 750khz operation. floating this pin selects 550khz operation. connect a 2.2nf capacitor between this pin and gnd and a 1000pf capacitor between this pin and the sync/mode when using spread spectrum modulation operation. sync/mode (pin 2/pin 3): this pin performs four func- tions: 1) auxiliary winding feedback input, 2) external clock synchronization input for phase-locked loop, 3) burst mode, pulse skipping or forced continuous mode select, and 4) enable spread spectrum modulation opera- tion in pulse skipping mode. applying a clock with fre- quency between 250khz to 750khz causes the internal oscillator to phase-lock to the external clock and disables burst mode operation but allows pulse skipping at low load currents. to select burst mode operation at light loads, tie this pin to v in . grounding this pin selects forced continuous operation, which allows the inductor current to reverse. tying this pin to v fb selects pulse skipping mode. in these cases, the frequency of the internal oscillator is set by the voltage on the plllpf pin. tying to a voltage between 1.35v to v in C 0.5v enables spread spectrum modulation operation. in this case, an internal 2.6 a pull-down cur- rent source helps to set the voltage at this pin by tying a resistor with appropriate value between this pin and v in . do not leave this pin floating . track/ss (pin 3/pin 4): tracking input for the controller or optional external soft-start input. this pin allows the start-up of v out to track the external voltage at this pin using an external resistor divider. tying this pin to v in allows v out start-up with the internal 1ms soft-start clamp. an external soft-start can be programmed by connecting a capacitor between this pin and ground. do not leave this pin floating . (dfn/ssop) pgood (pin 4/pin 5): power good output voltage moni- tor open-drain logic output. this pin is pulled to ground when the voltage on the feedback pin v fb is not within 13.3% of its nominal set point. v fb (pin 5/pin 6): feedback pin. this pin receives the remotely sensed feedback voltage for the controller from an external resistor divider across the output. i th (pin 6/pin 7): current threshold and error amplifier compensation point. nominal operating range on this pin is from 0.7v to 2v. the voltage on this pin determines the threshold of the main current comparator. run (pin 7/pin 8): run control input. forcing this pin below 1.1v shuts down the chip. driving this pin to v in or releasing this pin enables the chip to start-up either by tracking the external voltage at the track/ss pin or with the internal/external soft-start, all based on the connection at the track/ss pin. iprg (pin 8/pin 10): three-state pin to select maximum peak sense voltage threshold. this pin selects the maxi- mum allowed voltage drop between the sense + and sense C or sw pins (i.e., the maximum allowed drop across the sense resistor or the external p-channel mosfet). tie to v in , gnd or float to select 204mv, 85mv or 125mv respectively. bg (pin 9/pin 11): bottom (nmos) gate drive output. this pin drives the gate of the external n-channel mosfet. this pin has an output swing from gnd to sense + . tg (pin 10/pin 12): top (pmos) gate drive output. this pin drives the gate of the external p-channel mosfet. this pin has an output swing from gnd to sense + . sense + (pin 11/pin 13): positive input to differential current comparator. also powers the gate drivers. nor- mally connected to the source of the external p-channel mosfet when the sense resistor is not used. otherwise, it is connected to the sense resistor. v in (pin 12/pin 14): chip signal power supply. this pin powers the entire chip except for the gate drivers. exter- nally filtering this pin with a lowpass rc network (e.g., r = 10 ? , c = 1 f) is suggested to minimize noise pickup, especially in high load current applications. 8 ltc3808 3808f uu u pi fu ctio s (dfn/ssop) sense (pin 13/pin 15): negative input to differential current comparator. normally is connected to the sw pin when the sense resistor is not used. when using a current sense resistor, connect the resistor between sense + and sense C and connect the source of the p-channel mosfet to the sense C pin. sw (pin 14/pin 16): switch node connection to inductor. this pin is also an input to the reverse current comparator. normally this pin is connected to the drain of the external p-channel mosfet, the drain of the external n-channel mosfet and the inductor. gnd (pin 15/pins 1, 9): ground connection for internal circuits, the gate drivers and the negative input to the reverse current comparator. the exposed pad (pin 15 in dfn package) must be soldered to the pcb ground. C + C + C + C + C + slope sense C sense + i prg clk icmp r s q anti-shoot- through gnd pv in pv in sense + tg bg ov uv i rev 0.68v 0.54v v fb fcb v ref 0.6v trk/ss fcb sleep burstdis 0.15v v in 0.3v gnd i th 3808 fd v fb r c c c sw l mp mn c out v out switching logic and blanking circuit r a r b C + + sw gnd C + eamp ricmp clk burstdis sync/mode plllpf ov uv uvsd i rev v co mux phase detector clock detect burst defeat trk/ss track/ss 1 a t = 1ms internal soft-start run v in v in c in pgood v in gnd 2.6 a 0.4v v in uvsd v ref 0.6v v in 0.7 a undervoltage lockout voltage reference fu ctio al diagra u u w 9 ltc3808 3808f operatio u main control loop the ltc3808 uses a constant frequency, current mode architecture. during normal operation, the top external p-channel power mosfet is turned on when the clock sets the rs latch, and is turned off when the current comparator (icmp) resets the latch. the peak inductor current at which icmp resets the rs latch is determined by the voltage on the i th pin, which is driven by the output of the error amplifier (eamp). the v fb pin receives the output voltage feedback signal from an external resistor divider. this feedback signal is compared to the internal 0.6v reference voltage by the eamp. when the load current increases, it causes a slight decrease in v fb relative to the 0.6v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. while the top p-channel mosfet is off, the bottom n-channel mosfet is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator ircmp, or the beginning of the next cycle. shutdown, soft-start and tracking start-up (run and track/ss pins) the ltc3808 is shut down by pulling the run pin low. in shutdown, all controller functions are disabled and the chip draws only 9 a. the tg output is held high (off) and the bg output low (off) in shutdown. releasing the run pin allows an internal 0.7 a current source to pull up the run pin to v in . the controller is enabled when the run pin reaches 1.1v. the start-up of v out is based on the three different connections on the track/ss pin. the start-up of v out is controlled by the ltc3808s internal soft-start when track/ss is connected to v in . during soft-start, the error amplifier eamp compares the feedback signal v fb to the internal soft-start ramp (instead of the 0.6v reference), which rises linearly from 0v to 0.6v in about 1ms. this allows the output voltage to rise smoothly from 0v to its final value while maintaining control of the inductor current. the 1ms soft-start time can be changed by connecting the optional external soft-start capacitor c ss between the track/ss and gnd pins. when the controller is enabled by releasing the run pin, the track/ss pin is charged up by an internal 1 a current source and rises linearly from 0v to above 0.6v. the error amplifier eamp compares the feedback signal v fb to this ramp instead, and regulates v fb linearly from 0v to 0.6v. when the voltage on the track/ss pin is less than the 0.6v internal reference, the ltc3808 regulates the v fb voltage to the track/ss pin instead of the 0.6v reference. therefore v out of the ltc3808 can track an external voltage v x during start-up. typically, a resistor divider on v x is connected to the track/ss pin to allow the start-up of v out to track that of v x . for coincident tracking during start-up, the regulated final value of v x should be larger than that of v out , and the resistor divider on v x has the same ratio as the divider on v out that is connected to v fb . see detailed discussions in the run and soft-start/ tracking functions in the applications information section. light load operation (burst mode operation, continuous conduction or pulse skipping mode) (sync/mode pin) the ltc3808 can be programmed for either high effi- ciency burst mode operation, forced continuous conduc- tion mode or pulse skipping mode at low load currents. to select burst mode operation, tie the sync/mode pin to v in . to select forced continuous operation, tie the sync/ mode pin to a dc voltage below 0.4v (e.g., gnd). tying the sync/mode to a dc voltage above 0.4v and below 1.2v (e.g., v fb ) enables pulse skipping mode. the 0.4v threshold between forced continuous operation and pulse skipping mode can be used in secondary winding regula- tion as described in the auxiliary winding control using sync/mode pin discussion in the applications informa- tion section. when the ltc3808 is in burst mode operation, the peak current in the inductor is set to approximate one-fourth of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the eamp will decrease the voltage on the i th pin. when the i th voltage drops below 0.85v, the internal sleep signal goes high and the external mosfet is turned off. (refer to functional diagram) 10 ltc3808 3808f in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc3808 draws. the load current is supplied by the output capacitor. as the output voltage decreases, the eamp increases the i th voltage. when the i th voltage reaches 0.925v, the sleep signal goes low and the controller resumes normal opera- tion by turning on the external p-channel mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode or pulse skipping operation, the inductor current is not allowed to reverse. hence, the controller operates discontinuously. the reverse current comparator ricmp senses the drain- to-source voltage of the bottom external n-channel mosfet. this mosfet is turned off just before the inductor current reaches zero, preventing it from going negative. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. the p-channel mosfet is turned on every cycle (constant frequency) regardless of the i th pin voltage. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and no noise at audio frequencies. when the sync/mode pin is clocked by an external clock source to use the phase-locked loop (see frequency selection and phase-locked loop), or is set to a dc voltage between 0.4v and several hundred mv below v in , the ltc3808 operates in pwm pulse skipping mode at light loads. in this mode, the current comparator icmp may remain tripped for several cycles and force the external p-channel mosfet to stay off for the same number of cycles. the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. however, it provides low current efficiency higher than forced continuous mode, but not nearly as high as burst mode operation. during start-up or an undervoltage condition (v fb 0.54v), the ltc3808 operates in pulse skipping mode (no current reversal allowed), regardless of the state of the sync/mode pin. short-circuit and current limit protection the ltc3808 monitors the voltage drop ? v sc (between the gnd and sw pins) across the external n-channel mosfet with the short-circuit current limit comparator. the allowed voltage is determined by: ? v sc(max) = a ? 90mv where a is a constant determined by the state of the iprg pin. floating the iprg pin selects a = 1; tying iprg to v in selects a = 5/3; tying iprg to gnd selects a = 2/3. the inductor current limit for short-circuit protection is determined by ? v sc(max) and the on-resistance of the external n-channel mosfet: i v r sc sc max ds on = ? () () once the inductor current exceeds i sc , the short current comparator will shut off the external p-channel mosfet until the inductor current drops below i sc . output overvoltage protection as further protection, the overvoltage comparator (ovp) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. when the feedback voltage on the v fb pin has risen 13.33% above the reference voltage of 0.6v, the external p-chan- nel mosfet is turned off and the n-channel mosfet is turned on until the overvoltage is cleared. frequency selection and phase-locked loop (plllpf and sync/mode pins) the selection of switching frequency is a tradeoff between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to main- tain low output ripple voltage. the switching frequency of the ltc3808s controllers can be selected using the plllpf pin. if the sync/mode is not being driven by an external clock source, the plllpf can be floated, tied to v in or tied to gnd to select 550khz, 750khz or 300khz, respectively. operatio u (refer to functional diagram) 11 ltc3808 3808f a phase-locked loop (pll) is available on the ltc3808 to synchronize the internal oscillator to an external clock source that connects to the sync/mode pin. in this case, a series rc should be connected between the plllpf pin and gnd to serve as the plls loop filter. the ltc3808 phase detector adjusts the voltage on the plllpf pin to align the turn-on of the external p-channel mosfet to the rising edge of the synchronizing signal. the typical capture range of the ltc3808s phase-locked loop is from approximately 200khz to 1mhz. spread spectrum modulation (sync/mode and plllpf pins) connecting the sync/mode pin to a dc voltage above 1.35v and several hundred mv below v in enables spread spectrum modulation (ssm) operation. an internal 2.6 a pull-down current source at sync/mode helps to set the voltage at the sync/mode pin for this operation by tying a resistor with appropriate value between sync/mode and v in . this mode of operation spreads the internal oscillator frequency f osc (= 550khz) over a wider range (460khz to 635khz), reducing the peaks of the harmonic output on a spectral analysis of the output noise. in this case, a 2.2nf filter cap should be connected between the plllpf pin and gnd and another 1000pf cap should be connected between plllpf and the sync/mode pin. the controller operates in pwm pulse skipping mode at light loads when spread spectrum modulation is selected. see more discussions in the spread spectrum modulation with sync/mode and plllpf pins in the applications information section. dropout operation when the input supply voltage (v in ) approaches the output voltage, the rate of change of the inductor current while the external p-channel mosfet is on (on cycle) decreases. this reduction means that the p-channel mosfet will remain on for more than one oscillator cycle if the inductor current has not ramped up to the threshold set by the eamp on the i th pin. further reduction in the input supply voltage will eventually cause the p-channel mosfet to be turned on 100%; i.e., dc. the output voltage will then be determined by the input voltage minus the voltage drop across the p-channel mosfet and the inductor. undervoltage lockout to prevent operation of the p-channel mosfet below safe input voltage levels, an undervoltage lockout is incorporated in the ltc3808. when the input supply voltage (v in ) drops below 2.25v, the external p- and n-channel mosfets and all internal circuits are turned off except for the undervoltage block, which draws only a few microamperes. peak current sense voltage selection and slope compensation (iprg pin) when the ltc3808 controller is operating below 20% duty cycle, the peak current sense voltage (between the sense + and sense C /sw pins) allowed across the external p- channel mosfet is determined by: ? = va vv sense max ith () ? C. 07 10 where a is a constant determined by the state of the iprg pin. floating the iprg pin selects a = 1; tying iprg to v in selects a = 5/3; tying iprg to gnd selects a = 2/3. the operatio u (refer to functional diagram) 12 ltc3808 3808f maximum value of v ith is typically about 1.98v, so the maximum sense voltage allowed across the external p-channel mosfet is 125mv, 85mv or 204mv for the three respective states of the iprg pin. however, once the controllers duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor (sf) given by the curve in figure 1. the peak inductor current is determined by the peak sense voltage and the on-resistance of the external p-channel mosfet: i v r pk sense max ds on = ? () () duty cycle (%) 10 sf = i/i max (%) 60 80 110 100 90 3808 f01 40 20 50 70 90 30 10 0 30 50 70 20 0 40 60 80 100 figure 1. maximum peak current vs duty cycle if a sense resistor is used, ? v sense(max) is the peak current sense voltage (between the sense + and sense C pins) across the sense resistor. the peak inductor is determined by the peak sense voltage and the resistance of the sense resistor: i v r pk sense max sense = ? () power good (pgood) pin a window comparator monitors the feedback voltage and the open-drain pgood output pin is pulled low when the feedback voltage is not within 10% of the 0.6v reference voltage. pgood is low when the ltc3808 is shut down or in undervoltage lockout. operatio u (refer to functional diagram) 13 ltc3808 3808f applicatio s i for atio wu uu the typical ltc3808 application circuit is shown on figure 11. external component selection for the controller is driven by the load requirement and begins with the selection of the inductor and the power mosfets. power mosfet selection the ltc3808s controller requires two external power mosfets: a p-channel mosfet for the topside (main) switch and a n-channel mosfet for the bottom (synchro- nous) switch. the main selection criteria for the power mosfets are the breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , reverse transfer capacitance c rss , turn-off delay t d(off) and the total gate charge q g . the gate drive voltage is the input supply voltage. since the ltc3808 is designed for operation down to low input voltages, a sublogic level mosfet (r ds(on) guaranteed at v gs = 2.5v) is required for applications that work close to this voltage. when these mosfets are used, make sure that the input supply to the ltc3808 is less than the absolute maximum mosfet v gs rating, which is typically 8v. the p-channel mosfets on-resistance is chosen based on the required load current. the maximum average load current i out(max) is equal to the peak inductor current minus half the peak-to-peak ripple current i ripple . the ltc3808s current comparator monitors the drain-to- source voltage v ds of the top p-channel mosfet, which is sensed between the sense + and sw pins. the peak inductor current is limited by the current threshold, set by the voltage on the i th pin, of the current comparator. the voltage on the i th pin is internally clamped, which limits the maximum current sense threshold ? v sense(max) to approximately 125mv when iprg is floating (85mv when iprg is tied low; 204mv when iprg is tied high). the output current that the ltc3808 can provide is given by: i v r i out max sense max ds on ripple () () () C = ? 2 where i ripple is the inductor peak-to-peak ripple current (see inductor value calculation). a reasonable starting point is setting ripple current i ripple to be 40% of i out(max) . rearranging the above equation yields: r v i for duty cycle ds on max sense max out max () () () ?% = ? < 5 6 20 however, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of r ds(on) to provide the required amount of load current: rsf v i ds on max sense max out max () () () ?? = ? 5 6 where sf is a scale factor whose value is obtained from the curve in figure 1. these must be further derated to take into account the significant variation in on-resistance with temperature. the following equation is a good guide for determining the required r ds(on)max at 25 c (manufacturers specifica- tion), allowing some margin for variations in the ltc3808 and external component values: rsf v i ds on max sense max out max t () () () ?.? ? ? = ? 5 6 09 the t is a normalizing term accounting for the tempera- ture variation in on-resistance, which is typically about 0.4%/ c, as shown in figure 2. junction-to-case tempera- ture t jc is about 10 c in most applications. for a maxi- mum ambient temperature of 70 c, using 80 c ~ 1.3 in the above equation is a reasonable choice. the n-channel mosfets on resistance is chosen based on the short-circuit current limit (i sc ). the ltc3808s short-circuit current limit comparator monitors the drain- to-source voltage v ds of the bottom n-channel mosfet, 14 ltc3808 3808f which is sensed between the gnd and sw pins. the short- circuit current sense threshold ? v sc is set approximately 90mv when iprg is floating (60mv when iprg is tied low; 150mv when iprg is tied high). the on-resistance of n- channel mosfet is determined by: r v i ds on max sc sc peak () () = ? the short-circuit current limit (i sc(peak) ) should be larger than the i out(max) with some margin to avoid interfering with the peak current sensing loop. on the other hand, in order to prevent the mosfets from excessive heating and the inductor from saturation, i sc(peak) should be smaller than the minimum value of their current ratings. a reason- able range is: i out(max) < i sc(peak) < i rating(min) therefore, the on-resistance of n-channel mosfet should be chosen within the following range: ? << ? v i r v i sc rating min ds on sc out max () () () where ? v sc is 90mv, 60mv or 150mv with iprg being floated, tied to gnd or v in respectively. the power dissipated in the mosfet strongly depends on its respective duty cycles and load current. when the ltc3808 is operating in continuous mode, the duty cycles for the mosfets are: top p-channel duty cycle = bottom n-channel duty cycle = v v vv v out in in out in C the mosfet power dissipations at maximum output current are: p v v irv icf p vv v ir top out in out max t ds on in out max rss bot in out in out max t ds on =+ = ??? ? ??? C ??? () () () () () 22 2 2 ? ? ? ? ???? ? ? ?? ???? ? ? ? ? ? ?? ?? ? ?? ??? ? ?? ? ??? ? ??? ?? ?? ?? ???? ? c) C50 t normalized on resistance 1.0 1.5 150 3808 f02 0.5 0 0 50 100 2.0 figure 2. r ds(on) vs temperature applicatio s i for atio wu uu 15 ltc3808 3808f v in > 5v) may work fine at lower voltages (e.g., 3.3v). selecting the n-channel mosfet is typically easier, since for a given r ds(on) , the gate charge and turn-on and turn- off delays are much smaller than for a p-channel mosfet. using a sense resistor a sense resistor r sense can be connected between sense + and sense C to sense the output load current. in this case, the source of the p-channel mosfet is connected to sense C pin and the drain is connected to sw pin of ltc3808. therefore the current comparator monitors the voltage developed across r sense instead of v ds of the p-channel mosfet. the output current that the ltc3808 can provide in this case is given by: i v r i out max sense max sense ripple () () C = ? 2 setting ripple current as 40% of i out(max) and using figure 1 to choose sf, the value of r sense is: rsf v i sense sense max out max = ? 5 6 ?? () () see the p-channel r ds(on) selection in power mosfet selection. variation in the resistance of a sense resistor is much smaller than the variation in on-resistance of the external mosfet. therefore the load current is well controlled with a sense resistor. however the sense resistor causes extra i 2 r losses in addition to the i 2 r losses of the mosfet. therefore, using a sense resistor lowers the efficiency of ltc3808, especially for large load current. operating frequency and synchronization the choice of operating frequency, f osc , is a trade-off between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switch- ing losses, both gate charge loss and transition loss. however, lower frequency operation requires more induc- tance for a given amount of ripple current. the internal oscillator for the ltc3808s controller runs at a nominal 550khz frequency when the plllpf pin is left floating and the sync/mode pin is not configured for spread spectrum operation. pulling the plllpf to v in selects 750khz operation; pulling the plllpf to gnd selects 300khz operation. alternatively, the ltc3808 will phase-lock to a clock signal applied to the sync/mode pin with a frequency between 250khz and 750khz (see phase-locked loop and fre- quency synchronization). to further reduce emi, the nominal 550khz frequency will be spread over a range with frequencies between 460khz and 635khz when spread spectrum modulation is enabled (see spread spectrum modulation with sync/mode and plllpf pins). inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductors peak-to-peak ripple current: i v v vv fl ripple out in in out osc = ? C ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max). note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l vv fi v v in out osc ripple out in C ? ? burst mode operation considerations the choice of r ds(on) and inductor value also determines the load current at which the ltc3808 enters burst mode operation. when bursting, the controller clamps the peak inductor current to approximately: i v r burst peak sense max ds on () () () ? = ? 1 4 applicatio s i for atio wu uu 16 ltc3808 3808f the corresponding average current depends on the amount of ripple current. lower inductor values (higher i ripple ) will reduce the load current at which burst mode operation begins. the ripple current is normally set so that the inductor current is continuous during the burst periods. therefore, i ripple i burst(peak) this implies a minimum inductance of: l vv fi v v min in out osc burst peak out in C ? ? () a smaller value than l min could be used in the circuit, although the inductor current will not be continuous during burst periods, which will result in slightly lower efficiency. in general, though, it is a good idea to keep i ripple comparable to i burst(peak) . inductor core selection once the value of l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forc- ing the use of more expensive ferrite, molypermalloy or kool m ? cores. actual core loss is independent of core size for a fixed inductor value, but is very dependent on the induc- tance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. core saturation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m . toroids are very space efficient, especially when several layers of wire can be used, while inductors wound on bobbins are generally easier to sur- face mount. however, designs for surface mount that do not increase the height significantly are available from coiltronics, coilcraft, dale and sumida. schottky diode selection (optional) the schottky diode d in figure 12 conducts current during the dead time between the conduction of the power mosfets. this prevents the body diode of the bottom n-channel mosfet from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. a 1a schottky diode is generally a good size for most ltc3808 applications, since it conducts a relatively small average current. larger diode results in additional transition losses due to its larger junction capacitance. this diode may be omitted if the efficiency loss can be tolerated. c in and c out selection in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle (v out /v in ). to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c in re ? ?C / quiredi i vvv v rms max out in out in () 12 this formula has a maximum value at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet the size or height requirements in the design. due to the high operating frequency of the ltc3808, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is applicatio s i for atio wu uu kool m is a registered trademark of magnetics, inc. 17 ltc3808 3808f satisfied, the capacitance is adequate for filtering. the output ripple ( ? v out ) is approximated by: ? + ? ? ? ? ? ? v i esr fc out ripple out ? ?? 1 8 where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increase with input voltage. setting output voltage the ltc3808 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in figure 3. the regulated output voltage is deter- mined by: vv r r out b a =+ ? ? ? ? ? ? 06 1 .? for most applications, a 59k resistor is suggested for r a . in applications where minimizing the quiescent current is critical, r a should be made bigger to limit the feedback divider current. if r b then results in very high impedance, it may be beneficial to bypass r b with a 50pf to 100pf capacitor c ff . once the controller is enabled, the start-up of v out is controlled by the state of the track/ss pin. if the track/ ss pin is connected to v in , the start-up of v out is con- trolled by internal soft-start, which slowly ramps the positive reference to the error amplifier from 0v to 0.6v, allowing v out to rise smoothly from 0v to its final value. the default internal soft-start time is around 1ms. the soft-start time can be changed by placing a capacitor between the track/ss pin and gnd. in this case, the soft- start time will be approximately: tc mv a ss ss = ? 600 1 where 1 a is an internal current source which is always on. when the voltage on the track/ss pin is less than the internal 0.6v reference, the ltc3808 regulates the v fb voltage to the track/ss pin voltage instead of 0.6v. therefore the start-up of v out can ratiometrically track an external voltage v x , according to a ratio set by a resistor divider at track/ss pin (figure 5a). the ratiometric relation between v out and v x is (figure 5c): v v r r rr rr out x ta a ab ta tb = + + ? applicatio s i for atio wu uu ltc3808 v fb v out r b c ff r a 3808 f03 figure 3. setting output voltage run and soft-start/tracking functions the ltc3808 has a low power shutdown mode which is controlled by the run pin. pulling the run pin below 1.1v puts the ltc3808 into a low quiescent current shutdown mode (i q = 9 a). releasing the run pin, an internal 0.7 a (at v in = 4.2v) current source will pull the run pin up to v in , which enables the controller. the run pin can be driven directly from logic as showed in figure 4. 3.3v or 5v 3808 f04 ltc3808 run ltc3808 run figure 4. run pin interfacing ltc3808 v fb v out v x track/ss r b r a 3808 f5a r tb r ta figure 5a. using the track/ss pin to track v x 18 ltc3808 3808f for coincident tracking (v out = v x during start-up), r ta = r a , r tb = r b v x should always be greater than v out when using the tracking function of track/ss pin. the internal current source (1 a), which is for external soft-start, will cause a tracking error at v out . for example, if a 59k resistor is chosen for r ta , the r ta current will be about 10 a (600mv/59k). in this case, the 1 a internal current source will cause about 10% (1 a/10 a ? 100%) tracking error, which is about 60mv (600mv ? 10%) referred to v fb . this is acceptable for most applications. if a better tracking accuracy is required, the value of r ta should be reduced. table 1 summarizes the different states in which the track/ss can be used. table 1. the states of the track/ss pin track/ss pin frequency capacitor c ss external soft-start v in internal soft-start resistor divider v out tracking an external voltage v x phase-locked loop and frequency synchronization the ltc3808 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the external p-channel mosfet to be locked to the rising edge of an external clock signal applied to the sync/mode pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen- tary current sources that charge or discharge the external filter network connected to the plllpf pin. the relation- ship between the voltage on the plllpf pin and operating frequency, when there is a clock signal applied to sync/ mode, is shown in figure 6 and specified in the electrical characteristics table. note that the ltc3808 can only be synchronized to an external clock whose frequency is within range of the ltc3808s internal vco, which is applicatio s i for atio wu uu time (5b) coincident tracking v x v out output voltage time 3808 f05b,c (5c) ratiometric tracking v x v out output voltage figure 5b and 5c. two different modes of output voltage tracking plllpf pin voltage (v) 0.2 0 frequency (khz) 0.7 1.2 1.7 3808 f06 2.2 200 400 600 800 1000 1200 figure 6. relationship between oscillator frequency and voltage at the plllpf pin when synchronizing to an external clock 19 ltc3808 3808f table 2. the states of the plllpf pin plllpf pin sync/mode pin frequency 0v dc voltage (<1.2v or v in ) 300khz floating dc voltage (<1.2v or v in ) 550khz v in dc voltage (<1.2v or v in ) 750khz rc loop filter clock signal phase-locked to external clock filter caps dc voltage (>1.35v and 21 ltc3808 3808f low input supply voltage although the ltc3808 can function down to below 2.4v, the maximum allowable output current is reduced as v in decreases below 3v. figure 10 shows the amount of change as the supply is reduced down to 2.4v. also shown is the effect on v ref . minimum on-time considerations minimum on-time, t on(min) is the smallest amount of time that the ltc3808 is capable of turning the top p-channel mosfet on. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle and high frequency applications may approach the minimum on-time limit and care should be taken to ensure that: t v fv on min out osc in () ? < if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc3808 will begin to skip cycles (unless forced continuous mode is selected). the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. the minimum on- time for the ltc3808 is typically about 210ns. however, as the peak sense voltage (i l(peak) ?r ds(on) ) decreases, the minimum on-time gradually increases up to about 260ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if forced continuous mode is selected and the duty cycle falls below the minimum on time requirement, the output will be regulated by overvoltage protection. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3808 circuits: 1) ltc3808 dc bias current, 2) mosfet gate charge current, 3) i 2 r losses and 4) transition losses. 1) the v in (pin) current is the dc supply current, given in the electrical characteristics, which excludes mosfet driver currents. v in current results in a small loss that increases with v in . 2) mosfet gate charge current results from switching the gate capacitance of the power mosfet. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from sense + to ground. the resulting dq/dt is a current out of sense + , which is typically much larger than the dc supply current. in continuous mode, i gatechg = f ? q p . 3) i 2 r losses are calculated from the dc resistances of the mosfets, inductor and/or sense resistor. in continuous mode, the average output current flows through l but is chopped between the top p-channel mosfet and the bottom n-channel mosfet. the mosfet r ds(on) and/or the resistance of the sense resistor multiplied by duty cycle can be summed with the resistance of l to obtain i 2 r losses. 4) transition losses apply to the external mosfet and increase with higher operating frequencies and input volt- ages. transition losses can be estimated from: transition loss = 2 ? v in 2 ? i o(max) ? c rss ? f other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% total additional loss. applicatio s i for atio wu uu input voltage (v) 75 normalized voltage or current (%) 85 95 105 80 90 100 2.2 2.4 2.6 2.8 3808 f10 3.0 2.1 2.0 2.3 2.5 2.7 2.9 v ref maximum sense voltage figure 10. line regulation of v ref and maximum sense voltage 22 ltc3808 3808f applicatio s i for atio wu uu checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( ? i load ) ? (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability prob- lem. opti-loop compensation allows the transient re- sponse to be optimized over a wide range of output capacitance and esr values. the i th series r c -c c filter (see functional diagram) sets the dominant pole-zero loop compensation. the i th external components showed in the figure on the first page of this data sheet will provide adequate compen- sation for most applications. the values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitor needs to be decided upon because the various types and values deter- mine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1 s to 10 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability. the gain of the loop will be increased by increas- ing r c and the bandwidth of the loop will be increased by decreasing c c . the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation com- ponents, including a review of control loop theory, refer to application note 76. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25) ? (c load ). thus a 10 f capacitor would be require a 250 s rise time, limiting the charging current to about 200ma. design example as a design example, assume v in will be operating from a maximum of 4.2v down to a minimum of 2.75v (powered by a single lithium-ion battery). load current requirement is a maximum of 2a, but most of the time it will be in a standby mode requiring only 2ma. efficiency at both low and high load currents is important. burst mode operation at light loads is desired. output voltage is 1.8v. the iprg pin will be left floating, so the maximum current sense threshold ? v sense(max) is approximately 125mv. maximumduty cycle v v out in min = () .% = 65 5 from figure 1, sf = 82%. rsf v i ds on max sense max out max t () () () ?.? ? ? . = ? = ? 5 6 09 0032 ? ? p-channel mosfet in si7540dp is close to this value. 23 ltc3808 3808f applicatio s i for atio wu uu the n-channel mosfet in si7540dp has 0.017 ? r ds(on) . the short circuit current is: i mv a sc = ? = 90 0 017 53 . . so the inductor current rating should be higher than 5.3a. the plllpf pin will be left floating, so the ltc3808 will operate at its default frequency of 550khz. for continuous burst mode operation with 600ma i ripple , the required minimum inductor value is: l v khz ma v v h min = ? ? ? ? ? ? ? = 18 550 600 1 18 275 188 . ? ? . . . a 6a 2.2 h inductor works well for this application. c in will require an rms current rating of at least 1a at temperature. a c out with 0.1 esr will cause approxi- mately 60mv output ripple. in most applications, the requirements for these capacitors are fairly similar. pc board layout checklist when laying out the printed circuit board, use the follow- ing checklist to ensure proper operation of the ltc3808. ? the power loop (input capacitor, mosfet, inductor, output capacitor) should be as small as possible and isolated as much as possible from ltc3808. ? put the feedback resistors close to the v fb pins. the i th compensation components should also be very close to the ltc3808. ? the current sense traces (sense + and sense C ) should be kelvin connections right at the p-channel mosfet source and drain. ? keeping the switch node (sw) and the gate driver nodes (tg, bg) away from the small-signal components, espe- cially the feedback resistors, and i th compensation components. 24 ltc3808 3808f typical applicatio s u 10 f 1 f v in 2.75v to 8v v out 1.8v 2a mp si3447bdv mn si3460dv 3808 f12 2 1 8 4 6 3 5 12 11 10 13 14 9 7 15 1m l 1.5 h 22k 118k 59k 10 ? d opt l: vishay ihld-2525cz-01 d: on semi mbrm120l (optional) 100pf 10nf 100pf c out 22 f x2 sync/mode v in sense + plllpf iprg pgood i th track/ss v fb tg sense C sw bg run gnd ltc3808ede figure 12. 750khz, synchronous dc/dc converter with external soft-start, ceramic output capacitor 10 f 1 f v in 2.75v to 8v v out 2.5v (5a at 5v in ) mp si7540dp mn si7540dp 3808 f11 2 1 8 4 6 3 5 12 11 10 13 14 9 7 15 1m l 1.5 h 15k r ith 187k 59k 10 ? l: vishay ihld-2525cz-01 c out : sanyo 4tpb150mc 220pf c ith 10k 10nf 100pf c out 150 f sync/mode v in sense + plllpf iprg pgood i th track/ss v fb tg sense C sw bg run gnd ltc3808ede + figure 11. 550khz, synchronous dc/dc converter with internal soft-start 25 ltc3808 3808f 10 f 1 f v in 2.75v to 8v v out 1.8v (5a at 5v in ) mp si7540dp mn si7540dp 3808 ta02 2 1 8 4 6 3 5 12 11 10 13 14 9 7 15 1m 10k l 1.5 h 15k 1.18k 118k 100pf 59k 590 ? 10 ? l: vishay ihlp-2525cz-01 c out : sanyo 4tpb150mc v out < vx 220pf 10nf c out 150 f sync/mode v in sense + plllpf iprg pgood i th track/ss v fb tg sense C sw bg vx run gnd ltc3808ede + 10 f 1 f v in 2.75v to 8v v out 1.5v 2a mp si4431bdy mn si4860dy 3808 ta03 2 1 8 4 6 3 5 12 11 10 13 14 9 7 15 1m 301k l 1.5 h 15k 88.7k 100pf 59k 0.03 ? r sense 10 ? l: vishay ihlp-2525cz-01 c out : sanyo 4tpb150mc r sense : dale 0.25w 220pf 10nf 1000pf 2200pf c out 150 f sync/mode v in sense + plllpf iprg pgood i th track/ss v fb tg sense C sw bg run gnd ltc3808ede + typical applicatio s u synchronizable, synchronous dc/dc converter with output tracking resistor sensing, synchronous dc/dc converter with spread spectrum modulation 26 ltc3808 3808f u package descriptio de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708) 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.70 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 3.30 0.10 (2 sides) 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (de14) dfn 1203 0.25 0.05 pin 1 notch 0.50 bsc 3.30 0.05 (2 sides) recommended solder pad pitch and dimensions 1.70 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05 27 ltc3808 3808f u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 28 ltc3808 3808f ? linear technology corporation 2005 lt/tp 0305 500 ? printed in the usa part number description comments ltc1628/ltc3728 dual high efficiency, 2-phase synchronous constant frequency, standby, 5v and 3.3v ldos, v in to 36v, step down controllers 28-lead ssop ltc1735 high efficiency synchronous step-down controller burst mode operation, 16-pin narrow ssop, fault protection, 3.5v v in 36v ltc1772 constant frequency current mode step-down 2.5v v in 9.8v, i out up to 4a, sot-23 package, 550khz dc/dc controller ltc1773 synchronous step-down controller 2.65v v in 8.5v, i out up to 4a, 10-lead msop ltc1778 no r sense , synchronous step-down controller current mode operation without sense resistor, fast transient response, 4v v in 36v ltc1872 constant frequency current mode step-up controller 2.5v v in 9.8v, sot-23 package, 550khz ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out = 0.8v, i q = 60ma, i sd = <1ma, ms package ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out = 0.8v, i q = 60ma, i sd = <1ma, tssop-16e package ltc3416 4a, 4mhz, monolithic synchronous step-down regulator tracking input to provide easy supply sequencing, 2.25v v in 5.5v, 20-lead tssop package ltc3701 2-phase, low input voltage dual step-down dc/dc controller 2.5v v in 9.8v, 550khz, pgood, pll, 16-lead ssop LTC3708 2-phase, no r sense , dual synchronous controller with constant on-time dual controller, v in up to 36v, very low output tracking duty cycle operation, 5mm 5mm qfn package ltc3736 2-phase, no r sense , dual synchronous controller with 2.75v v in 9.8v, 0.6v v out v in , 4mm 4mm qfn output tracking ltc3736-1 low emi 2-phase, dual synchronous controller with integrated spread spectrum for 20db lower emi, output tracking 2.75v v in 9.8v ltc3737 2-phase, no r sense , dual dc/dc controller with output tracking 2.75v v in 9.8v, 0.6v v out v in , 4mm 4mm qfn polyphase is a trademark of linear technology corporation. related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com typical applicatio s u 550khz, pulse-skipping mode, synchronous dc/dc converter with ceramic output capacitor c vin 1 f r vin 10 ? c in 22 f v in 3.3v v out 2.5v 2a mp si3447bdv mn si3460dv 3808 ta04 1 8 4 3 6 2 5 12 11 13 10 14 9 7 15 l 1.5 h r ith 22k 187k 59k l: vishay ihlp-2525cz-01 c ith 470pf c out 22 f 2x plllpf v in sense + iprg pgood track/ss i th sync/mode v fb sense C tg sw bg run gnd ltc3808ede |
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